1. Field of the Invention
This invention relates to computing systems and, more particularly, to multithreaded processing systems.
2. Description of the Related Art
Multi-core chips have become increasingly popular in recent years. In order to take advantage of these multi-core chips, efforts to parallelize sequential applications may be undertaken. One approach to parallelization is compiler based automatic parallelization which attempts to parallelize programs, either sequential or explicitly parallel, automatically. For example, given a loop, if the compiler can prove that there exists no inter-loop data dependences, the loop can be parallelized. Otherwise, the loop may not be parallelized. Because the compiler has to be conservative to ensure correctness, there are loops which actually do not have inter-loop data dependence but are not parallelized because the compiler cannot prove there is no inter-loop data dependence. If such loops could somehow be parallelized, additional speedup may be achieved at runtime.
Hardware transactional memory, for which development is under investigation by several vendors, is a hardware extension to support better multi-threaded application development. Various research projects have demonstrated transactional memory can greatly reduce lock contention and hence improve multi-threaded application performance. However, little research has been done on transactional memory to help parallelize programs. Previous efforts have investigated a compiler framework to generate code for speculative automatic parallelization with hardware transactional memory. For example, thread-level speculation (TLS) has been proposed as a means to parallelize difficult-to-analyze serial codes. While speculative thread-level automatic parallelization has the potential to improve performance, uncontrolled parallelization may hurt performance if the parallelization overhead is greater than the benefit. In view of the above, effective methods and mechanisms for improving parallelization efforts are desired.
In view of the above, effective methods and mechanisms for improving parallelization efforts are desired.